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Intel Details Upcoming Mobile and Six-Core Processors

February 4th, 2010 No comments

Intel Details Upcoming Mobile and Six-Core Processors – HotHardware


With the International Solid-State Circuits Conference less than a week away, Intel has released additional details on its hexa-core desktop, next generation mobile and dual-core Westmere processors. Much of the dual-core data was revealed last month when the CPU manufacturer launched Clarkdale (our review is here if you want additional information on the CPU and its integrated graphics core). When Intel set its internal goals for what its calling Westmere 6C, the company aimed to boost both core and cache count by 50 percent without increasing the processor’s thermal envelope. Towards this end, the new Westmere chips will incorporate additional technologies to reduce the CPU’s power consumption at idle.

Westmere 6C (codename Gulftown) is a native six-core chip as shown above. Intel has crammed 1.17 billion transistors into a die that’s approximately 240mm sq. The new chip carries 12MB up L3 (up from Nehalem’s 8MB) and a TDP of 130W at 3.33GHz. In addition to the addition of hardware AES encryption instruction decode support, Intel has made a number of improvements to Gulftown’s power consumption. Up until now, Intel’s efforts to reduce CPU power consumption focused on what it calls the “Core” the “Uncore” hardware couldn’t be powered down or controlled to the same degree. Starting with Westmere, both sections of the CPU can be fine-tuned to minimize power consumption without adversely affecting processor performance. As part of its bid to increase CPU complexity and performance without driving up system-level power consumption, Westmere will also support low-voltage DDR3, which uses an operating voltage of 1.35v (down from 1.5v standard). According to Intel, using the lower voltage memory reduces memory power consumption by about 20 percent overall.

Mobile


The big mobile-specific tech that Intel has debuted with Arrandale (32nm Westmere 2C) is a Turbo Boost for graphics mode. While Intel’s standard Turbo mode is available as well, the chip can also cut CPU frequency and ramp the IGP higher to improve graphics performance. Intel refers to this as “HD Graphics with dynamic frequency.” How much of a boost this mode can deliver depends on which processor you’ve got. Intel’s spec sheets for the Core i3 processor list a 500MHz standard frequency with a 667MHz maximum dynamic frequency while the Core i5 mobile parts top out at 766MHz. That’s 1.33x and 1.53x above stock, respectively.


There are two ways to take Intel’s Dynamic Frequency technology. On the one hand, it’s true that Intel’s integrated GPUs have historically been terrible choices for gaming; what the parts have lacked in hardware functionality, they’ve made up for in terrible driver support. Arrandale’s integrated IGP is more advanced than any of its desktop predecessors, but the “new” features Intel baked into the on-die GPU, such as hierarchical Z support, are technologies ATI and NVIDIA launched nearly nine years ago. Trailing your competition is one thing, trailing your competition by a decade is something else entirely.

On the other hand, however, Intel’s new IGP is indisputably the fastest, most gaming-friendly part the company has ever built. A 33 percent (or 53 percent) higher clockspeed isn’t going to turn Arrandale’s IGP into a discrete part from ATI or NVIDIA, but it should provide noticable performance improvements provided that the processor speed tradeoff doesn’t obscure them. The ability to trade CPU cycles for GPU horsepower gives even a modest system additional flexibility; it’s easy to see how this sort of capability could end up integrated into Intel’s Atom product line in the not-too-distant future.

And Now For Something Completely Different

In addition to its x86 CPU briefings, Intel will present a number of paper’s at the ISSCC. Chief among these are the company’s ongoing research into so-called “digital intelligence,” high-speed point-to-point interconnects, and reconfigurable computing. Intel will also give more details on a 48-core single-chip processor it unveiled last December. One of the features the company will discuss is the chip’s use of so-called circuit switching rather than packet switching when passing messages. By mapping out the route from core to core before actually sending a message, Intel claims it can vastly accelerate the speed at which information is passed within the chip structure.
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Intel Details Upcoming Mobile and Six-Core Processors

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Intel demos first-ever 32nm processors

February 11th, 2009 No comments

Intel had a little roadmap event today to shed some light on its massive $7b fab investment, and the focus was mostly on the upcoming transition to 32nm processors — highlighted by the first-ever demo of a working 32nm Nehalem-based Westmere chip. It was just a demo, so there aren’t any hard benchmarks available, but eventually the tech will show up in the Calpella platform’s dual-core Clarkdale laptop processors that integrate two processor cores, a graphics core, and a memory controller all in a chip the size of one 45nm quad-core Clarksfield chip. (Yes, the codenames are confusing as hell.) Intel wouldn’t lock down the schedule for any of this stuff, but when we asked them about the rumored Calpella delays we heard about this morning we were told that parts of the platform will definitely go into production sometime in 2009. Video, slides, and the full press release after the break.

Intel Demonstrates First Working 32nm-based Microprocessor
in Both Mobile and Desktop Systems

Feb. 10, 2009 – At a media briefing in San Francisco today, Intel Corporation discussed new milestones for 32nm manufacturing and progress toward future products. Earlier that day, in Washington, DC, Intel President and CEO Paul Otellini disclosed that Intel is making the largest- ever investment in a single process technology in the United States to support upgrades to advanced manufacturing facilities in the country and the move to its next-generation, 32nm chip manufacturing technology. Intel is investing approximately $7 billion in 2009-10 on 32nm manufacturing technology, raising the total by the end of that timeframe to approximately $8 billion (for 32nm investment in the United States).

Below is a summary of the product roadmap news at the briefing in San Francisco:

First-ever demonstration of a working 32nm-based microprocessor:

  • Intel is demonstrating the first 32nm working microprocessor in both mobile and desktop systems.
  • Great 32nm process and product health are enabling Intel to accelerate 32nm product ramp
    • Westmere mobile and desktop processor production in the fourth quarter of 2009
    • 32nm enables increased performance and power flexibility
  • Intel processors based on Westmere will ramp into mobile, desktop, and server segments over time, as the 32nm process ramps

For client, Westmere brings Nehalem through Intel’s mainstream processor product line

  • Increased performance, smaller processor core size
  • New multi-chip package with graphics integrated in the processor
  • Repartitioned system architecture, simplified motherboards
  • Volume ramp; expect 32nm in server market in 2010

Westmere key features

  • Intel® Turbo Boost technology
  • Intel® Hyper-Threading technology (2 Cores, 4 threads)
  • Integrated graphics, discrete/switchable graphics support
  • 4MB cache, Integrated Memory Controller (IMC) – 2ch DDR3
  • AES Instructions

The 32nm process with second-generation high-k + metal gate transistor era begins
Intel’s strength as an integrated device manufacturer allows the company to continue to deliver new generations of advanced process technology on a 2-year cadence. Intel has developed a 32nm logic technology with industry-leading features:

  • Second-generation high-k + metal gate transistors
  • 32nm marks the first time Intel uses immersion lithography on critical layers
  • 9 copper + low-k interconnect layers
  • About 70 percent dimension scaling from 45nm generation
  • Pb- and halogen-free packages

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Intel demos first-ever 32nm processors

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